The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment

FPGA-based ASIC development systems have become important tools in contemporary ASIC design. Existing systems exhibit low per-FPGA gate utilization (10 to 20 percent) due to limited inter-chip communication. Attempts at overcoming this limitation through the use of high dimensional interconnection topologies have met with limited success. This paper focuses on the prototype hardware and software interfaces that have been developed for an FPGA-based ASIC emulation system based on a new technique for overcoming inter-chip communication limitations. This technique, referred to as virtual wires, intelligently multiplexes each physical FPGA wire among a number of logical wires. The Virtual Wires Emulation System exhibits high FPGA gate utilization while achieving system speeds comparable to existing logic emulators. A two-dimensional mesh interconnection topology of FPGAs is used to eliminate the cost of signal switching elements and to facilitate scalability. A system capable of emulating 20,000 gates has been constructed for under $3000. This system includes both prototype emulation hardware and a Virtual Wires netlist compiler. Currently, this system is being used as both a simulation accelerator for the LSI Logic LSIM and Cadence Verilog simulators and as an in-circuit emulator. Results from mapping netlists, such as the 18K gate Sparcle microprocessor [2], to this system for simulation acceleration and in-circuit emulation indicate that virtual wires can substantially increase FPGA utilization without adversely affecting emulation speed.